Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

• Published in: IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 pp. 893 - 896
• Main Authors: CHANG WOO OH, SUNG DAE SUK, MING LI, SUNG HWAN KIM, YOON, Eun-Jung, KIM, Dong-Won, PARK, Donggun, KIM, Kinam, RYU, Byung-Il, YONG KYU LEE, SUK KANG SUNG, CHOE, Jung-Dong, LEE, Sung-Young, DONG UK CHOI, KYOUNG HWAN YEO, MIN SANG KIM, KIM, Sung-Min
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004
• Subjects: Applied sciences; CMOS process; Controllability; Design. Technologies. Operation analysis. Testing; Electronics; Etching; Exact sciences and technology; Fabrication; FinFETs; Flash memory; Integrated circuits; Integrated circuits by function (including memories and processors); Microelectronic fabrication (materials and surfaces technology); Research and development; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; SONOS devices; Threshold voltage; Transistors; Voltage threshold; MOSFET; Mass storage; Retention factor; Dual gate transistor; Erasure; SONOS structure; Damascene process; Overvoltage; Self aligned technology; Microelectronic fabrication; Non volatile memory; Integrated circuit; Chemical mechanical polishing; Wafer
• ISBN: 0780386841; 9780780386846
• DOI: 10.1109/IEDM.2004.1419324

We successfully demonstrate highly scaled damascene gate FinFET SONOS memory implemented on bulk silicon wafer. The FinFET SONOS devices show extremely high program/erase speed, large threshold voltage shifts over 4V at 1/spl mu/s/12V for program and 50/spl mu/s/-12V for erase, good retention time, and acceptable endurance. Thus, in sub-50nm regimes, ultra high speed operation becomes possible by using FinFET SONOS structure without sacrificing retention time.