Design-for-Test for Intermittent Faults in STT-MRAMs

• Published in: 2024 IEEE European Test Symposium (ETS) pp. 1 - 6
• Main Authors: Yuan, Sicong, Yaldagard, Mohammad Amin, Xun, Hanzhi, Fieback, Moritz, Marinissen, Erik Jan, Kim, Woojin, Rao, Siddharth, Couet, Sebastien, Taouil, Mottaqiallah, Hamdioui, Said
• Format: Conference Proceeding
• Language: English
• Published: IEEE 20.05.2024
• Subjects: defect; design for test; Design for testability; Discrete Fourier transforms; fault; MTJ; Production; Random access memory; Simulation; stochasticity; STT-MRAM; Switches; test development; Torque
• ISSN: 1558-1780
• DOI: 10.1109/ETS61313.2024.10567702

Guaranteeing high-quality test solutions for Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a must to speed up its high-volume production. A high test quality requires maximizing the fault coverage. Detecting permanent faults is relatively simple compared to intermittent faults; the latter are faults (caused by non-environmental conditions) that appear and disappear as a function of time, and are therefore hard to detect. Testing for such faults in STT-MRAMs is even worse considering the Magnetic Tunneling Junction inherent property 'intrinsic switching stochasticity', which results in inevitable random write errors. This paper presents a novel Design-for-Testability (DFT) scheme for detecting intermittent faults in STT-MRAMs; it is based on monitoring the write current. The strength of the write current is inversely correlated to the write error rate; when the write current is smaller than the specification, the device is considered faulty. A reduction in the write current can be caused by any defect in the write path of the memory (e.g., interconnects and contacts). Simulation results based on industrial design show that applying DFT yields a superior coverage of intermittent faults compared to functional test methods, such as march tests.