Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express® 6.0

• Published in: 2023 IEEE Symposium on High-Performance Interconnects (HOTI) pp. 1 - 8
• Main Authors: Sharma, Debendra Das, Choudhary, Swadesh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2023
• Subjects: Availability; Cyclic redundancy check; FIT; Forward error correction; Integrated circuit interconnections; Logic gates; PCI-Express; Programmable logic arrays; Registers; Reliability; Replay; Spectral efficiency
• ISSN: 2332-5569
• DOI: 10.1109/HOTI59126.2023.00015

PCI Express ® (PCIe ® ) specification has been doubling the data rate every generation in a backward compatible manner every three years. PCIe 6.0 specification will adopt PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach, cost, and power profile as prior generations. A Forward Error Correction (FEC) mechanism will offset the high BER of PAM-4. A strong Cyclic Redundancy Check (CRC) and a link level replay mechanism will deliver a low-latency, high bandwidth efficiency, and highly reliable solution expected of a Load-Store interconnect. We propose a non-pipelined implementation of the FEC and CRC that is part of the PCIe 6.0 base specification. We also propose a partitionable and pipelined implementation for FEC and CRC for lowering gate count and latency. We have tested the correctness of our register transfer logic (RTL) implementation in a field programmable gate array (FPGA) implementation in addition to simulation. Synthesis results from the Synopsys DC compiler demonstrates that for a x16 PCIe Link partitionable to up to x4s, with 4 independent controllers using independently partitionable logic, we achieve a gate count of about 100,000 for the transmit and receive side with a FEC + CRC delay of less than 1 nano second (nsec) in each direction.