Improvement on the Gate Oxide Integrity Caused by the TUB Charges in SOI Technology

Silicon-On-Insulator (SOI) technology is fabricated on substrate with Buried OXide layer (BOX). It offers high performance for noise and power consumption with high device density. This paper describes the journey of understanding and improving the Gate Oxide Integrity (GOI) for SOI technology. Inve...

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Bibliographic Details
Published in2024 35th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) pp. 01 - 04
Main Authors Ying Ying, Lesley Wong, Anak Tuloi, Charissa Antia, Pilkington, Steven John, Hun Jin, Ryan Lee, Zhong Hong, Desmond Lau
Format Conference Proceeding
LanguageEnglish
Published IEEE 13.05.2024
Subjects
02 plasma
charges
cleaning efficiency
Logic gates
Oxidation
Performance evaluation
Plasmas
Resists
Semiconductor device manufacture
Silicon-on-insulator
wettability
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Summary:Silicon-On-Insulator (SOI) technology is fabricated on substrate with Buried OXide layer (BOX). It offers high performance for noise and power consumption with high device density. This paper describes the journey of understanding and improving the Gate Oxide Integrity (GOI) for SOI technology. Investigation shows a strong influence from the charges within a TUB to the GOI performance. The TUB is a WELL region formed by Deep Trench Isolation (DTI) and the BOX layer. The TUB charges are influenced by the processes in the ONO (Oxide- Nitride-Oxide) process loop. The charges affect the surface bonding which defines the surface wettability and hence the cleaning efficiency. Using O2 plasma treatment to modify the surface bonding is proven to improve the GOI performance.
ISSN:2376-6697
DOI:10.1109/ASMC61125.2024.10545493