A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs

• Published in: 2024 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
• Main Authors: Wang, Yaning, Li, Zhenguo, Wang, Peng, Cheng, Yihang, Li, Fule, Hu, Yi, Hou, Jiali, Su, Meng, Li, Mengjiao
• Format: Conference Proceeding
• Language: English
• Published: IEEE 19.05.2024
• Subjects: Capacitors; Circuit stability; CMOS process; Common-mode stability; FIA; High-speed ADCs; Power supplies; PVT-robust; Ring-amp; Robustness; Stability analysis; Voltage
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS58744.2024.10558189

This paper presents a floating-ring hybrid amplifier (FRHA) insensitive to PVT and common-mode variation, in which a floating power supply is used for the third stage. In differential-mode, the transistors of third stage are forced into the subthreshold region, which improves the loop gain and quickly realizes the pole separation, reducing the times of the oscillation convergence. As for common-mode, a pair of small cross-coupled NMOS is added as the load of first stage, which sharply reduced the common-mode gain without affecting the differential-mode gain much. Moreover, the floating power supply provided by the capacitor has natural common-mode stability. To achieve PVT robustness, a PVT tracking circuit for charging the power supply capacitor is designed, which solves the early shutdown of the third stage caused by insufficient capacitor charge at fast process corner and reduces oscillation cycles due to insufficient phase margin at slow process corner. This FRHA has been applied to a 12-bit 200MS/s pipelined-SAR ADC as residue amplifier (RA) in 65nm CMOS process. The simulation result achieves 67.95dB SNDR at Nyquist frequency and 1.2Vpeak-peak input, yielding a Walden FoM of 5.57 fJ/con-step.