Method of Scalable Polysilicon Resistor by Adjusting Shielding Metal in CMOS Process

The sheet resistance of polysilicon resistors has been investigated with a split design of metal shielding to the polysilicon resistor body. The design split includes metal level split, shielding metal extension size split to resistor body, and metal shielding ratio to a poly resistor in 0.18um CMOS...

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Bibliographic Details
Published in2024 Conference of Science and Technology for Integrated Circuits (CSTIC) pp. 1 - 3
Main Authors Lee, Hun Jin, Kim, Hyeon Cheol
Format Conference Proceeding
LanguageEnglish
Published IEEE 17.03.2024
Subjects
CMOS process
Integrated circuits
Metals
Process control
Resistance
Resistors
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Summary:The sheet resistance of polysilicon resistors has been investigated with a split design of metal shielding to the polysilicon resistor body. The design split includes metal level split, shielding metal extension size split to resistor body, and metal shielding ratio to a poly resistor in 0.18um CMOS process. Based on the evaluation results, we found that it's possible to control the sheet resistance of poly resistors by metal-1 shielding design, which allows a scalable polysilicon resistor with different polysilicon sheet resistance with the exact dimensions without any process change or addition. Therefore, the chip designer can control the polysilicon sheet resistance considering the available design area for the resistor. Finally, it will be helpful to minimize the chip size, which will lead to a cost-effective design.
DOI:10.1109/CSTIC61820.2024.10531972