FitBit: Ensuring Robust and Secure Execution Through Runtime-Generated Stressmarks

• Published in: 2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) pp. 194 - 198
• Main Authors: Swaminathan, Karthik, Bertran, Ramon, Buyuktosunoglu, Alper, Bose, Pradip
• Format: Conference Proceeding
• Language: English
• Published: IEEE 06.05.2024
• Subjects: Benchmark testing; Computer viruses; Microarchitecture; Runtime; Side-channel attacks; Switches; Wearable Health Monitoring Systems
• ISSN: 2765-8406
• DOI: 10.1109/HOST55342.2024.10545416

Processor reliability and security are fast becoming key design constraints alongside performance and energy efficiency. Efficient techniques for monitoring processor vulner-ability to hard and soft errors, and to security threats such as malware, side-channel attacks and power viruses, are becoming increasingly prevalent across all computing domains. In this paper, we present FitBit, a design for runtime detection of Unit-level Power Viruses (UPVs), or malicious programs aimed at stressing one or more microarchitecture units in the core, as well as Silent Data Corruptions (SDCs) that can affect security keys, cryptographic hashes and other critical elements within the processor. To achieve this, FitBit leverages runtime-generated stressmarks tuned to a particular application or set of applications slated to run on the processor, which are termed as Workload-Specific Stressmarks (WSS). Our experiments demon-strate a 2 x increase in switching activity in WSS over SPEC CPU 2017 benchmarks, and enable us to improve the probability of SDC detection by 8 x compared to standard benchmarks.