A receiver architecture for intra-band carrier aggregation

A block downconversion receiver incorporates a digital image rejection technique to support multiple aggregated carriers by one receive path and one frequency synthesizer. A prototype consisting of a CMOS RF front end and an FPGA back end exhibits an image rejection ratio (IRR) of at least 70 dB acr...

Full description

Saved in:
Bibliographic Details
Published in2014 Symposium on VLSI Circuits Digest of Technical Papers pp. 1 - 2
Main Authors Sy-Chyuan Hwu, Razavi, Behzad
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2014
Subjects
Logic gates
Mixers
Radio frequency
Online AccessGet full text

Cover

More Information
Summary:A block downconversion receiver incorporates a digital image rejection technique to support multiple aggregated carriers by one receive path and one frequency synthesizer. A prototype consisting of a CMOS RF front end and an FPGA back end exhibits an image rejection ratio (IRR) of at least 70 dB across 2 GHz ± 25 MHz and reconstructs a -76-dBm 64-QAM signal with an EVM of -30 dB in the presence of another channel 40 dB higher.
ISBN:9781479933273
1479933279
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2014.6858418