A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-ch...

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Bibliographic Details
Published in2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers pp. 182 - 183,183a
Main Authors Yong Liu, Byungsub Kim, Dickson, T.O., Bulzacchelli, J.F., Friedman, D.J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2009
Subjects
Backplanes
Cables
Circuits
CMOS technology
Decision feedback equalizers
Frequency measurement
Loss measurement
Silicon
Testing
Very large scale integration
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Summary:The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-chip interconnect, will make I/O area and power requirements even more stringent.This paper describes an alternative low-power compact I/O transceiver with RX equalization that achieves the required multi-bit postcursor cancellation without a high tap-count DFE. While this work targets data transmission over Si carrier links at rates up to 10Gb/s, it is also relevant to backplane channels.
ISBN:9781424434589
1424434580
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2009.4977368