Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET

• Published in: 2021 IEEE International Symposium on Circuits and Systems (ISCAS) p. 1
• Main Authors: Shavit, Netanel, Stanger, Inbal, Taco, Ramiro, Lanuzza, Marco, Fish, Alexander
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2021
• Subjects: Computer architecture; Digital signal processing; FinFETs; Silicon; Switches; Time measurement
• ISBN: 9781728192017; 1728192013
• ISSN: 2158-1525; 2158-1525
• DOI: 10.1109/ISCAS51556.2021.9401241

The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16×16-bit Booth multiplier fabricated as a part of an ultra-low power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same design saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.