A Computational Efficient Architecture for Extremely Sparse Stereo Network

CNN-based stereo matching methods achieve great performance but come with high computational requirements. Pruning a CNN can reduce the complexity but may in turn lead to memory conflicts, lowering throughput. Our proposed architecture and memory mapping technique aim at reducing conflicts to exploi...

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Bibliographic Details
Published in2021 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
Main Authors Huang, Tan, Wu, Sih-Sian, Klopp, Jan, Yu, Po-Hsiang, Chen, Liang-Gee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2021
Subjects
Computer architecture
deconvolution
Memory architecture
Memory mapping
Neural networks
PE utilization
Random access memory
Shape
Software
sparsity-aware CNN
Throughput
VLSI architecture
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Summary:CNN-based stereo matching methods achieve great performance but come with high computational requirements. Pruning a CNN can reduce the complexity but may in turn lead to memory conflicts, lowering throughput. Our proposed architecture and memory mapping technique aim at reducing conflicts to exploit extremely sparse stereo matching networks. To maintain a high utilization of processing elements, we decompose the de-convolution operation into several convolution operations. The proposed architecture provides a 2.1 x speed up over SCNN. Compared to the software implementation, only 0.01% performance drop is observed, so that the proposed architecture obtains state-of-the-art accuracy compared to existing sparsity aware hardware implementations.
ISBN:9781728192017
1728192013
ISSN:2158-1525
2158-1525
DOI:10.1109/ISCAS51556.2021.9401565