Junctionless Nanowire Transistor for Analog Applications: Cascode Current Mirror Configuration

In this paper, a cascode current mirror compounded by junctionless nanowire transistors is analyzed for the first time. Thus, the performance and the mirroring precision of the configuration were investigated considering the internal circuit feedback and the high output resistance. On this basis, sy...

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Bibliographic Details
Published in2022 36th Symposium on Microelectronics Technology (SBMICRO) pp. 1 - 4
Main Authors Shibutani, Andr B., Trevisoli, Renan, Doria, Rodrigo T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 22.08.2022
Subjects
Behavioral sciences
Cascode Current Mirror
Circuit optimization
Current mirrors
Current transfer ratio
Feedback circuits
JNT
Microelectronics
Resistance
SOI Technology
Transistors
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Summary:In this paper, a cascode current mirror compounded by junctionless nanowire transistors is analyzed for the first time. Thus, the performance and the mirroring precision of the configuration were investigated considering the internal circuit feedback and the high output resistance. On this basis, symmetrical and asymmetrical configurations were examined to comprehend the junctionless nanowire transistor behavior as a current source.
DOI:10.1109/SBMICRO55822.2022.9881034