A 5th-order Configurable-Frequency Direct Delta-Sigma Converter for Mobile Application

This paper presents a novel design of direct delta-sigma receiver, which is different from conventional design. This receiver is designed to cover Frequency Division Duplex (FDD) bands from 0.4 GHz to 3.6 GHz with a configurable bandwidth of 3.84 MHz (WCDMA), and 9.0/13.5/18/37 MHz (LTE-10M/15M/20M/...

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Bibliographic Details
Published in2019 International Conference on Advanced Technologies for Communications (ATC) pp. 292 - 296
Main Authors Bui, Thanh-Phong, Ngo, Chi-Trung, Nguyen, Binh-Minh, Pham, Van-Khanh, Nguyen-Due, Minh, Pham-Nguyen, Loan, Nguyen, Van-Tam
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2019
Subjects
Bandwidth
Capacitors
Continuous time
delta-sigma
Linearity
Long Term Evolution
multi-band
multi-standard
Noise measurement
oversampling
Radio frequency
Receivers
RF ADC
RF sampling
wideband receiver
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Summary:This paper presents a novel design of direct delta-sigma receiver, which is different from conventional design. This receiver is designed to cover Frequency Division Duplex (FDD) bands from 0.4 GHz to 3.6 GHz with a configurable bandwidth of 3.84 MHz (WCDMA), and 9.0/13.5/18/37 MHz (LTE-10M/15M/20M/37M). The receiver complies with 3GPP specification while performing Noise Figure (NF) of 2.5dB, Inband (IB) Third-order intercept point (IIP3) of -15dBm, Out-of-band (OOB) IIP3 of OdBm and peak Signal-to-Noise-and-Distortion ratio (SNDR) of 58dB. The circuit is designed in CMOS 65nm, and the power consumption is 70 mA at a voltage supply of 1.2 V.
ISSN:2162-1039
DOI:10.1109/ATC.2019.8924552