Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node

Continued scaling of the interconnect geometry increases the metal resistance which degrades the performance of SRAM in advanced technology nodes. We propose an energy-efficient multi-tiers monolithic 3D (M3D) SRAM cell design with stacked 2D material nanosheet FETs to release the impact of metal li...

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Bibliographic Details
Published in2021 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
Main Authors Hu, Vita Pi-Ho, Su, Cheng-Wei, Yu, Chun-Chi, Liu, Chang-Ju, Weng, Cheng-Yang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2021
Subjects
2-D material
area efficiency
energy efficiency
Field effect transistors
Metals
Molybdenum
monolithic 3-D (M3D)
Resistance
SRAM
SRAM cells
Sulfur
Three-dimensional displays
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Summary:Continued scaling of the interconnect geometry increases the metal resistance which degrades the performance of SRAM in advanced technology nodes. We propose an energy-efficient multi-tiers monolithic 3D (M3D) SRAM cell design with stacked 2D material nanosheet FETs to release the impact of metal line resistance. Considering the 2nm node design rules, the 3-tier M3D SRAM cell with stacked MoS2 FETs shows a 42% reduction in cell area, 49% improvement in read access time, and 68% improvement in energy-delay product. The energy- and area-efficient high-performance 3- tier M3D SRAM cell enables intelligent functionalities for the area and energy-constrained edge computing devices.
ISBN:9781728192017
1728192013
ISSN:2158-1525
2158-1525
DOI:10.1109/ISCAS51556.2021.9401245