Experimental validation of a chip area optimized 3.3 kV SiC half bridge for HVDC converters

The content of this paper demonstrates the experi-mental validation of a semiconductor area optimized 3.3 kV SiC half bridge for HVDC converters. The core of this work is a comparison on sub module level between the conventional half bridge and the asymmetric HVDC specific half bridge, which feature...

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Bibliographic Details
Published in2022 IEEE Applied Power Electronics Conference and Exposition (APEC) pp. 1645 - 1652
Main Authors Bergmann, Lukas, Wahle, Marcus, Bakran, Mark-M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 20.03.2022
Subjects
Bridge circuits
Costs
HVDC
HVDC transmission
MMC
MOSFET
Silicon carbide
Silicon Carbide (SiC)
Switches
Switching loss
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Summary:The content of this paper demonstrates the experi-mental validation of a semiconductor area optimized 3.3 kV SiC half bridge for HVDC converters. The core of this work is a comparison on sub module level between the conventional half bridge and the asymmetric HVDC specific half bridge, which features an asymmetrical semiconductor area between high side and low side switch. The main motivation of this approach is to save costly SiC semiconductor area and exploit the asymmetrical stress of low side and high side switches in the sub modules of a Modular Multilevel Converter (MM C). The system level design is already published and therefore, only the basics it will be presented. The focus is on switching characteristics of the MOSFET and the freewheeling body diode. The impact of design methods on dead time optimization, switching over-voltage, reverse recovery behavior, current slope and switching losses is investigated.
ISSN:2470-6647
DOI:10.1109/APEC43599.2022.9773514