Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors

• Published in: 2022 IEEE 35th International System-on-Chip Conference (SOCC) pp. 1 - 6
• Main Authors: Kempf, Fabian, Hoefer, Julian, Kres, Fabian, Hotfilter, Tim, Harbaum, Tanja, Becker, Juergen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05.09.2022
• Subjects: Checkpointing; Fault detection; Hardware; Multicore processing; Reduced instruction set computing; Runtime; Software
• ISSN: 2164-1706
• DOI: 10.1109/SOCC56010.2022.9908110

In the future, it is expected that safety-critical and non-critical applications are executed on the same hardware. Therefore, future hardware systems should be capable of providing runtime support for higher reliability requirements of safety-critical applications and higher performance requirements of noncritical applications equally. In this paper, we present a run-time adaptive cache with a coarse-grained safety mechanism to tackle this emerging challenge. For non-critical applications, the cache operates in a performance mode without any safety mechanisms. On the other hand, the cache checkpointing mechanism with a rollback feature for fault recovery are used for safety-critical applications. The hardware supports a reconfiguration form one mode to the other where no software adaptations are required. The complete reconfiguration process between the performance mode and the reliable mode is hidden from the software.We demonstrate the applicability of our adaptive caches in a RISC multi-core processor. Therefore, a prototype based on the LEON3 open source RISC processor is developed. The executed benchmarks show a low execution overhead introduced by the adaptive cache checkpointing. Furthermore, injected faults are successfully handled by the fault detection and recovery mechanism.