Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology

In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuits in 28nm fully depleted silicon-on-insulator (FD-SOI) technology. The combination of the flexibility of Dual Mode Logic (DML) and the unique characteristics of the FD-SOI technology has enormous po...

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Bibliographic Details
Published in2020 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
Main Authors Taco, Ramiro, Yavits, Leonid, Shavit, Netanel, Stanger, Inbal, Lanuzza, Marco, Fish, Alexander
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2020
Subjects
adaptive energy-efficient digital design
Adders
Delays
dual mode logic
Energy consumption
FD-SOI
Logic gates
Topology
Transistors
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Summary:In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuits in 28nm fully depleted silicon-on-insulator (FD-SOI) technology. The combination of the flexibility of Dual Mode Logic (DML) and the unique characteristics of the FD-SOI technology has enormous potential to design energy-efficient adaptive digital circuits operating on an ultra-wide voltage range. As a main result, we demonstrate that single well option offered by the FD-SOI greatly extends the low-granularity energy-delay (E-D) optimization capability of DML-based designs. By exploiting the above implementation strategy, a 16-bit DML carry skip adder reduces its energy consumption by 41% and increases its speed of about 26% when changing its operation mode (from static to dynamic) at 0.4V as compared to its equivalent standard CMOS design.
ISBN:9781728133201
1728133203
ISSN:2158-1525
2158-1525
DOI:10.1109/ISCAS45731.2020.9180449