Thermal Challenges and Design Considerations in Heterogeneous Integrated Through-Silicon-interposer Platform for III-V HEMT Flip Chip

• Published in: 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) pp. 1030 - 1035
• Main Authors: Chen, Haoran, Lim, Teck Guan, Tang, Gongyue
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2022
• Subjects: 2.5D heterogeneous integration; Correlation; Couplings; Electronic packaging thermal management; Gallium arsenide; HEMTs; III-V HEMT flip chips; thermal analysis; thermal coupling strength; Thermal resistance; Three-dimensional displays; through. Silicon interposer
• ISSN: 2377-5726
• DOI: 10.1109/ECTC51906.2022.00168

This paper presents the numerical study about the thermal characteristics of a compact, heterogeneously integrated flip-chip gallium nitride on silicon carbide (GaN-on-SiC) and gallium arsenide (GaAs) and through-silicon- interposer (TSI) assembly. A full-scale 3D finite element model is developed for a 100mm 2 TSI platform carrying GaAs low noise amplifiers of above 50W/cm 2 , GaN-on-SiC power amplifier of above 100W/cm 2 level and thermal sensitive passive filters for RF receive and transmit front-end. Thermal simulations are conducted to determine how the heat transfer and temperature distribution in the lateral and vertical directions are affected by thermal interconnects, metal heat spreaders and thermal interfaces. The complex correlation between thermal resistance and thermal coupling strength in these thermal designed structures are studied by applying entransy theory. Thermal design guidelines for flip-chip mounted GaN-on-SiC or GaAs chips with air-bridge are proposed based on die size, dissipation power density, junction temperature limit and external cooling condition. An example of thermal design to enhance heat dissipation capacity of the flip-chip TSI heterogeneous integration platform while reducing thermal crosstalk will be presented in details using the obtained correlation and the developed method. This work provides useful information to aid in designing high performance and reliability package with heterogeneously integrated III-V HEMT flip chip on TSI platform.