Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs

As the development of binary systems forecasted to reach to its end, ternary system is gaining more attention. However, most ternary logic circuits were not considered to be a 'true' competitor to binary systems. To counter this common belief on ternary logic, in this study, we propose a t...

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Bibliographic Details
Published in2022 IEEE 52nd International Symposium on Multiple-Valued Logic (ISMVL) pp. 21 - 26
Main Authors Lee, Hyundong, Jang, Hyeseung, Yun, Jihyeong, Jin, Huijeen, Kim, Jongbeom, Kim, Yeji, Song, Taigon
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2022
Subjects
balanced ternary full adder
Depletion-mode MOSFET
Logic design
Logic gates
Memristors
MOSFET
Multivalued logic
Power demand
ternary logic
Transistors
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Summary:As the development of binary systems forecasted to reach to its end, ternary system is gaining more attention. However, most ternary logic circuits were not considered to be a 'true' competitor to binary systems. To counter this common belief on ternary logic, in this study, we propose a ternary logic system based on depletion-mode MOSFETs and conventional MOSFETs that can truly compete with binary systems in terms of power and delay. Based on our novel circuitry of 11 logic gates, we illustrate that (1) our circuits consume near-zero static current on all logic states (−1, 0, +1), (2) our standard ternary inverter (STI) shows improved PDP of 71× and 245× compared to conventional CNTFET or memristor and MOSFET based ternary circuits, and (3) our balanced ternary full adder (BTFA) shows 48× improved power consumption compared to other ternary-device based adders and 5.3× improved power compared to the same devices. With our results, we highlight that ternary logic is now competitive to binary.
ISSN:2378-2226
DOI:10.1109/ISMVL52857.2022.00011