Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation

• Published in: 2022 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1823 - 1827
• Main Authors: Caselli, Michele, Bhattacharjee, Debjyoti, Mallik, Arindam, Debacker, Peter, Verkest, Diederik
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28.05.2022
• Subjects: Deep learning; Energy consumption; Energy efficiency; Energy resolution; Network topology; Neural networks; Silicon
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS48785.2022.9937613

This paper presents a tiny charge injection-Successive Approximation (ci-SAR) A/D converter (ADC) to be integrated at the periphery of analog Matrix Vector Multiplication (MVM) accelerators for Deep Neural Network (DNN) inference. Derived from the ci-SAR ADC, this converter exploits a single charge injecting cell to minimize area and energy consumption. The ADC exhibits a signal-to-noise and distortion ratio of 30.5 dB, at 5 bits of nominal resolution. The energy per conversion is 86 fJ, running at 34 MS/s, with a silicon area of 75 \mu m ^{2}, in 22 nm technology node. From the results of our analytical framework, an SRAM-based Analog in-Memory Compute (AiMC) array, including the proposed ADC at 5 bits of resolution, can achieve an energy efficiency of 1650 TOPs/W.