Enhanced Floating-Point Adder with Full Denormal Support

This paper presents an enhanced floating-point adder (FADD) design for the Intel E-Core processor. Floating-point addition and subtraction are two of the most widely used operations in many applications. The proposed FADD is executed in 2 cycles, fully pipelined, handles SSE/AVX operations for scala...

Full description

Saved in:
Bibliographic Details
Published in2022 IEEE 29th Symposium on Computer Arithmetic (ARITH) pp. 01 - 08
Main Authors Sohn, Jongwook, Dean, David K., Quintana, Eric, Wong, Wing Shek
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2022
Subjects
Adders
Delays
Digital arithmetic
Floating-point adder
floating-point arithmetic
floating-point denormal numbers
high-speed computer arithmetic
Next generation networking
Optimization
Online AccessGet full text

Cover

More Information
Summary:This paper presents an enhanced floating-point adder (FADD) design for the Intel E-Core processor. Floating-point addition and subtraction are two of the most widely used operations in many applications. The proposed FADD is executed in 2 cycles, fully pipelined, handles SSE/AVX operations for scalar/packed IEEE single and double precision, and supports all four rounding modes. Also, the proposed FADD fully supports both denormal inputs and underflow outputs without microcode assistance. To achieve the 2-cycle FADD with full denormal support, several optimization techniques are applied: split path algorithm, early alignment and sticky logic, parallel addition, rounding and all-ones detection, and modified leading zero anticipation (LZA) for masking the underflow. As a result, the proposed FADD achieved not only full denormal support but also about 12.5% reduced latency compared to the traditional FADD designs.
ISSN:2576-2265
DOI:10.1109/ARITH54963.2022.00015