Reliability Qualification Challenges of SOCs in Advanced CMOS Process Nodes (Invited)

We discuss the reliability methodology and risk mitigation for qualification and reliability of SOCs in advanced Finfet technology nodes. Determining SOC mission profile through field data collection is demonstrated from a practical case as a first step towards developing an efficient qualification...

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Bibliographic Details
Published in2022 IEEE International Reliability Physics Symposium (IRPS) pp. 8A.1-1 - 8A.1-6
Main Authors Liu, Shou-En, Li, Jian, Nayak, Deepak, Marathe, Amit, Balamukundhan, Kaushik, Gosavi, Vishal, Prajapati, Ajaykumar, Kilic, Baha, Pang, Mengzhi, Mittal, Arpit
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2022
Subjects
advanced Finfet technology
board-level reliability
FinFETs
HTOL testing
mission profile
Packaging
Product qualification
Reliability
Risk management
Semiconductor device modeling
SOC
Stress
Temperature distribution
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Summary:We discuss the reliability methodology and risk mitigation for qualification and reliability of SOCs in advanced Finfet technology nodes. Determining SOC mission profile through field data collection is demonstrated from a practical case as a first step towards developing an efficient qualification methodology. The challenges of HTOL testing in advanced process nodes are discussed and the mitigation methodology is presented. It is shown that an accurate mission profile is of paramount importance to achieve target lifetime and FIT from the HTOL testing. Finally, the influence of new package technology on the reliability qualification SOCs is analyzed via FEA simulation and board-level reliability experimental data.
ISSN:1938-1891
DOI:10.1109/IRPS48227.2022.9764426