Scalable representation of dataflow graph structures using topological patterns

• Published in: 2010 IEEE Workshop On Signal Processing Systems pp. 13 - 18
• Main Authors: Sane, N, Hojin Kee, Seetharaman, G, Bhattacharyya, S S
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2010
• Subjects: Arrays; Dataflow graphs; Digital signal processing; Field programmable gate arrays; high-level languages; modelbased design; Semantics; signal processing systems; topological patterns; Topology; Transform coding
• ISBN: 1424489326; 9781424489329
• ISSN: 2162-3562; 2162-3570
• DOI: 10.1109/SIPS.2010.5624821

Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interface (GUI) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the DIF language - a language for specifying DSP-oriented dataflow graphs - with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.