Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow

Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in high level synthesis. Delay relaxation that assigns extra clock latencies to functional resources at RTL (register transfer...

Full description

Saved in:
Bibliographic Details
Published in2007 Design, Automation & Test in Europe Conference & Exhibition pp. 1 - 6
Main Authors Chuan Lin, Aiguo Xie, Hai Zhou
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2007
Subjects
Clocks
Costs
Delay
Design automation
High level synthesis
Integrated circuit interconnections
Pipeline processing
Polynomials
Registers
Timing
Online AccessGet full text

Cover

More Information
Summary:Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in high level synthesis. Delay relaxation that assigns extra clock latencies to functional resources at RTL (register transfer level) can be leveraged. This paper proposed a general formulation for design closure driven delay relaxation problem. The authors show that the general formulation can be transformed into a convex cost integer dual network flow problem and solved in polynomial time using the convex cost-scaling algorithm in (Ahuja et al., 2003). Experimental results validate the efficiency of the approach
ISBN:3981080122
9783981080124
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2007.364568