Estimating Functional Coverage in Bounded Model Checking

• Published in: 2007 Design, Automation & Test in Europe Conference & Exhibition pp. 1 - 6
• Main Authors: Grobe, D., Kuhne, U., Drechsler, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2007
• Subjects: Boolean functions; Circuits and systems; Computer science; Context modeling; Data structures; Formal verification; Reduced instruction set computing; Signal analysis; Signal generators; State-space methods
• ISBN: 3981080122; 9783981080124
• ISSN: 1530-1591; 1558-1101
• DOI: 10.1109/DATE.2007.364454

Formal verification is an important issue in circuit and system design. In this context, bounded model checking (BMC) is one of the most successful techniques. But even if all specified properties can be verified, it is difficult to determine whether they cover the complete functional behavior of a design. We propose a pragmatic approach to estimate coverage in BMC. The approach can easily be integrated in a BMC tool with only minor changes. In our approach, a coverage property is generated for each important signal. If the considered properties do not describe the signal's entire behavior, the coverage property fails and a counter-example is generated. From the counter-example an uncovered scenario can be derived. In this way the approach also helps in design understanding. Our method is demonstrated on a RISC CPU. Based on the results we identified coverage gaps. We were able to close all of them and achieved 100% functional coverage