Developments for the PANDA online high level trigger

• Published in: 2010 17th IEEE-NPSS Real Time Conference pp. 1 - 7
• Main Authors: Münchow, D, Qiang Wang, Dapeng Jin, Kühn, W, Lange, J Sören, Yutie Liang, Ming Liu, Zhen'an Liu, Spruck, Björn, Hao Xu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2010
• Subjects: Algorithm design and analysis; cluster finding; Clustering algorithms; Detectors; Electromagnetic compatibility; Electromagnetics; EMC; Field programmable gate arrays; FPGA; high level online trigger; MVD; PANDA; Physics; STT; tracking
• ISBN: 1424471087; 9781424471089
• DOI: 10.1109/RTC.2010.5750453

The PANDA detector is a state-of-the-art general-purpose detector for physics with high luminosity cooled antiproton beams, planed to operate at the FAIR facility in Darmstadt, Germany. The central detector includes a silicon Micro Vertex Detector (MVD) and a Straw Tube Tracker (STT) or Time Projection Chamber (TPC). The electromagnetic lead tungstate calorimeter(EMC) provides almost 4π spatial coverage, good granularity and high energy resolution for electromagnetic showers measurement. A DIRC Cherenkov detector serves for particle identification. A novel trigger-less data push data architecture for the PANDA trigger and data acquisition system is proposed requiring the data from readout module to be processed in real-time to reconstruct charged tracks, electromagnetic showers and calculating PID parameters. This presentation shows results from the development of online high level trigger algorithms. A track finding algorithm for helix track reconstruction in the solenoidal field and a cluster finder for searching clusters in the EMC have been developed with special considerations for the implementation on the FPGA based Compute Node platform which has been developed for PANDA. Performance parameters such as momentum and spatial resolution for the helix track finder, energy and spatial resolution for the EMC cluster finder will be presented. With respect to the FPGA implementation, the partition strategy based on the readout electronics layout and the Compute Node processing architecture will be presented.