Fault modeling and testable design of 2-level complex ECL gates
Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behaviour of 2-level complex ECL gates is examined in the presence of physical faults. It is shown that the conventional stuck-at fault model cannot represent a majority of circ...
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Published in | [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design pp. 23 - 28 |
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Main Authors | , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE Comput. Soc. Press
1991
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Subjects | |
Online Access | Get full text |
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Summary: | Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behaviour of 2-level complex ECL gates is examined in the presence of physical faults. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. A testable design approach is presented for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices.< > |
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ISBN: | 9780818621253 0818621257 |
DOI: | 10.1109/ISVD.1991.185087 |