Design for testability and test generation with two clocks

Proposes a novel design for testability method that enhances the controllability of storage elements by use of additional clock lines. The scheme is applicable to synchronous circuits but is otherwise transparent to the designer. The associated area and speed penalties are minimal compared to scan b...

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Bibliographic Details
Published in[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design pp. 112 - 117
Main Authors Agrawal, V.D., Seth, S.C., Deogun, J.S.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1991
Subjects
Automatic test pattern generation
Circuit faults
Circuit testing
Clocks
Controllability
Counting circuits
Design for testability
Flip-flops
Sequential analysis
System testing
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Summary:Proposes a novel design for testability method that enhances the controllability of storage elements by use of additional clock lines. The scheme is applicable to synchronous circuits but is otherwise transparent to the designer. The associated area and speed penalties are minimal compared to scan based methods. However, a sequential ATPG system is necessary for test generation. The basic idea is to use independent clock lines to control disjoint groups of flip-flops. No cyclic path is permitted among the flip-flops of the same group. During testing, a selected group can be made to hold its state by disabling its clock lines. In the normal mode, all clock lines carry the same system clock signal. With the appropriate partitioning of flip-flops, the length of the vector sequence produced by the test generator for a fault is drastically reduced. An n-stage binary counter is used for experimental verification of reduction in test length by the proposed technique.< >
ISBN:9780818621253
0818621257
DOI:10.1109/ISVD.1991.185102