Design of Low Power On-chip Processor Arrays

In this paper, we present an ultra low power design for a class of massively parallel architectures, called tightly-coupled processor arrays.Here, the key idea is to exploit the benefits of a decentralized resource management as inherent to invasive computing for power saving.We propose concepts and...

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Bibliographic Details
Published in2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors pp. 165 - 168
Main Authors Lari, V., Muddasani, S., Boppu, S., Hannig, F., Teich, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2012
Subjects
Computer architecture
Energy consumption
Hardware
Parallel processing
Phasor measurement units
Process control
Program processors
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Summary:In this paper, we present an ultra low power design for a class of massively parallel architectures, called tightly-coupled processor arrays.Here, the key idea is to exploit the benefits of a decentralized resource management as inherent to invasive computing for power saving.We propose concepts and studying different architecture trade-offs for hierarchical power management by temporarily shutting down regions of processors through power gating. Moreover, a) overall system chip energy consumption, b) hardware cost, and c) timing overheads are compared for different sizes of power domains.Experimental results show that up to 70\,\% of system energy consumption may be saved for selected characteristical algorithms and different resource utilizations.
ISBN:9781467322430
1467322431
ISSN:1063-6862
DOI:10.1109/ASAP.2012.10