Novel procedure to improve LDMOS ESD characteristics by optimizing drain structure

• Published in: 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD) pp. 179 - 182
• Main Authors: Komatsu, Kanako, Takahashi, Keita, Sakurai, Tadaomi, Ikimura, Takehito, Sakai, Masaki, Kimura, Koji, Matsuoka, Fumitomo
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.06.2016
• Subjects: Breakdown; Contact; Drains; Electric fields; Electric potential; Electronic ballasts; Electrostatic discharges; Lattices; Optimization; Power semiconductor devices; Resistance; Robustness; Three-dimensional displays; Voltage
• DOI: 10.1109/ISPSD.2016.7520807

Novel procedure to realize a high ESD robustness with small variation for 40V p-ch LDMOS is proposed. By optimizing the drain structure, current flow path detaches from highest electric field point during ESD events, which leads to improve both HBM robustness and its variation. By using this procedure, the device length (the length between drain and source contact) increase could be suppressed from 37 % to 8 % compared with another approach which introduced ballast resistance in the drain. The studied 40V p-ch LDMOS achieved over 6200 V HBM performance keeping the drain-source breakdown voltage (|BVdss|) over 46 V.