Novel procedure to improve LDMOS ESD characteristics by optimizing drain structure

Novel procedure to realize a high ESD robustness with small variation for 40V p-ch LDMOS is proposed. By optimizing the drain structure, current flow path detaches from highest electric field point during ESD events, which leads to improve both HBM robustness and its variation. By using this procedu...

Full description

Saved in:
Bibliographic Details
Published in2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD) pp. 179 - 182
Main Authors Komatsu, Kanako, Takahashi, Keita, Sakurai, Tadaomi, Ikimura, Takehito, Sakai, Masaki, Kimura, Koji, Matsuoka, Fumitomo
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 01.06.2016
Subjects
Breakdown
Contact
Drains
Electric fields
Electric potential
Electronic ballasts
Electrostatic discharges
Lattices
Optimization
Power semiconductor devices
Resistance
Robustness
Three-dimensional displays
Voltage
Online AccessGet full text

Cover

More Information
Summary:Novel procedure to realize a high ESD robustness with small variation for 40V p-ch LDMOS is proposed. By optimizing the drain structure, current flow path detaches from highest electric field point during ESD events, which leads to improve both HBM robustness and its variation. By using this procedure, the device length (the length between drain and source contact) increase could be suppressed from 37 % to 8 % compared with another approach which introduced ballast resistance in the drain. The studied 40V p-ch LDMOS achieved over 6200 V HBM performance keeping the drain-source breakdown voltage (|BVdss|) over 46 V.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Conference-1
ObjectType-Feature-3
content type line 23
SourceType-Conference Papers & Proceedings-2
ISSN:1946-0201
DOI:10.1109/ISPSD.2016.7520807