Address interleaving for low-cost NoCs

• Published in: 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) pp. 1 - 8
• Main Authors: Grammatikakis, Miltos D., Papadimitriou, Kyprianos, Petrakis, Polydoros, Coppola, Marcello, Soulie, Michael
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2016
• Subjects: address decoding; address interleaving; Irrigation; link-width; network interface (NI); Network-on-Chip (NoC); saturation; throughput
• DOI: 10.1109/ReCoSoC.2016.7533892

New generations of NoC-based platforms incorporate address interleaving, which enables balancing transactions between the memory nodes. The memory space is distributed in different nodes of the NoC, and accessed alternately by each on-chip initiator. A memory node is accessed depending on the transaction request address through a memory map. Interleaving can allow for efficient use of NoC bandwidth and congestion reduction, and we study whether its gains scale over system size. In this work we concentrate on an instance of a customizable point-to-point interconnect from STMicroelectronics called STNoC. We first evaluate a setup with 4 CPU initiators and 4 memories, and show that interleaving relieves the NoC from congestion and permits higher packet injection rates. We also show that this depends on the number of packets sent per transaction by an initiator prior to changing destination memory node; this is called interleaving step. We then enriched the setup with several DMA engines, which is in accordance with industry roadmap. We experimented with MPSoCs having up to 32-nodes and for various link-widths of the STNoC. When link-width was 32 Bytes, the aggregate throughput gain from address interleaving was 20.8%, but when we set it 8 Bytes the throughput gain reached 69.64%. This implies silicon savings in SoCs, as it is not always necessary to configure NoCs with wide link-widths.