A 320MHz–2.56GHz low jitter phase-locked loop with adaptive-bandwidth technique

• Published in: 2015 28th IEEE International System-on-Chip Conference (SOCC) pp. 40 - 43
• Main Authors: Seok Min Jung, Roveda, Janet Meiling
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.09.2015
• Subjects: adaptive-bandwidth; Bandwidth; Clocks; closed loop voltage controlled oscillator (VCO); CMOS integrated circuits; Conferences; Constants; Gain; Iterative closest point algorithm; Jitter; Phase locked loops; phase-locked loop (PLL); System on chip; Unity; Voltage controlled oscillators
• ISSN: 2164-1706
• DOI: 10.1109/SOCC.2015.7406906

This paper presents a novel adaptive-bandwidth phase-locked loop (PLL) using a closed loop voltage controlled oscillator (VCO). The adaptive-bandwidth PLL uses the gain of closed loop VCO to obtain a constant unity gain bandwidth over an operating frequency range. Furthermore, a charge pump (CP) current is proportional to the current of VCO so that CP current is in proportion to the VCO frequency. Since the adaptive-bandwidth is optimized over the VCO frequency, an integrated RMS jitter is reduced in comparison to a conventional fixed-bandwidth PLL. We simulate the proposed PLL in 130 nm CMOS technology at 1.2 V power supply. The integrated RMS jitter of the proposed adaptive-bandwidth PLL is 2.35 psec which is 70% smaller than the conventional PLL. This adaptive-bandwidth PLL consumes 2.6 mW at 2.56 GHz output frequency.