Chip to wafer bonding for three-dimensional integration of copper low K Chip by stacking process

• Published in: 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013) pp. 250 - 254
• Main Authors: Ser Choong Chong, Jie Li Aw, Ching, Eva Wai Leong, Cereno, Daniel Ismael, Hong Yu Li, Vempati, Srinivasa Rao, Keng Hwa Teo
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2013
• Subjects: Bonding; Electronics packaging; Materials; Soldering; Stacking; Through-silicon vias; Wafer bonding
• DOI: 10.1109/EPTC.2013.6745722

Industry is adopting three-dimensional integration of Cu-low k Chip with micro-solder bumps by stacking process to increase the functionality and performance of the device. Cu/low k is known to be very fragile and required special packaging process to prevent early delamination issues. Stacking of thin chips with micro-solder bumps need to be carried out without causing solder squeezing, solder non-wetting and also die crack due to improper bonding parameters. In this study, six Cu/low k chips were bonded to another Cu/low k wafer using wafer level pre-applied underfill. The chip used is of size 12mm × 12mm × 0.07mm and consists of peripheral micro-solder bumps at 80μm pitch with SnAg solder cap. The chips were pre-coated with wafer level underfill. Bonding process parameters were evaluated and the optimum parameters determined for the six die stack assembly. Entrapment of underfill material inside the solder material was observed in the bonded samples and this issue was overcome by removing the underfill material above the solder bump through surface planarisation. The developed die stacking successfully demonstrated on C2W application.