Design of 60-GHz 90-nm CMOS balanced power amplifier with miniaturized quadrature hybrids

This paper presents a 60-GHz CMOS balanced power amplifier (PA) with miniaturized quadrature hybrids using 90-nm CMOS technology. To improve the output power and provide an area-efficient solution for the balanced PA design, a compact 3-dB quadrature hybrid constructed by a broadside-coupled scheme...

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Bibliographic Details
Published in2014 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR) pp. 52 - 54
Main Authors Chien-Chih Lin, Chun-Han Yu, Hsin-Chih Kuo, Huey-Ru Chuang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2014
Subjects
60 GHz
Balanced amplifier
Circuit faults
CMOS
CMOS integrated circuits
CMOS technology
Gain
Hybrid power systems
Miniaturized quadrature hybrid
Power amplifier
Power amplifiers
Power generation
V-band
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Summary:This paper presents a 60-GHz CMOS balanced power amplifier (PA) with miniaturized quadrature hybrids using 90-nm CMOS technology. To improve the output power and provide an area-efficient solution for the balanced PA design, a compact 3-dB quadrature hybrid constructed by a broadside-coupled scheme is employed as a low-insertion-loss power splitter/combiner. With a very short effective guided wavelength of 0.072 λ g , the simulated insertion loss and phase difference of the quadrature hybrids are better than 0.5 dB and 90° ± 0.2°, respectively. The designed PA reaches a power gain exceeding 13.2 dB and a saturation power of 10.7 dBm with a power-added efficiency (PAE) more than 9 % at 60 GHz. The power consumption of the PA is 109 mW at a 1.2 V supply voltage. The chip size is 0.68 mm 2 .
DOI:10.1109/PAWR.2014.6825723