A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition

• Published in: 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC) pp. 1 - 4
• Main Authors: Chao Yuan, Kian Ann Ng, Yong Ping Xu, Shih-Cheng Yen, Thakor, Nitish V.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2015
• Subjects: Arrays; Capacitance; Capacitors; Frequency measurement; Power demand; Semiconductor device measurement; Switches
• DOI: 10.1109/ASSCC.2015.7387509

This paper reports a high-performance low-power and area-efficient single-ended SAR ADC for neural signal acquisition. The proposed 10-bit ADC features a novel symmetrical DAC switching technique that resolves the signal-dependent comparator offset voltage problem in conventional single-ended SAR ADCs, and improves the ADC's ENOB. Combined with an existing LSB single-sided switching method, the proposed switching scheme reduces DAC switching energy by 92% and capacitor array area by 50%. Besides, the proposed ADC also eliminates the need for any power consuming Vcm generation circuit, making it more suitable for low-power System-on-Chip (SoC) integration. The 10-bit prototype ADC is fabricated in a standard 0.18-um CMOS technology. Operating at 1.0 V power supply and 100 kS/s, the proposed ADC achieves 58.83 dB SNDR and 63.6 dB SFDR for a 49.06 kHz input signal. The maximum ENOB is 9.8-bit for low frequency input signal; and the minimum ENOB is 9.48-bit at the Nyquist input frequency. The average power consumption is 1.72 μW and the fig re-of-merit (FoM) is 24.1 fJ/conversion-step.