Adiabatic constant delay logic style

• Published in: 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS) pp. 1 - 5
• Main Authors: Senthilkumaran, K., Kashwan, K. R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2015
• Subjects: ACD logic; Adders; CD logic; Clocks; Delays; digital blocks; full-custom; Power demand; Power dissipation; Propagation delay
• ISBN: 147996817X; 9781479968176
• DOI: 10.1109/ICIIECS.2015.7193025

An adiabatic constant delay (ACD) logic style is proposed in this paper, for full-custom high-speed and low power applications. The characteristic of ACD logic style will not depend upon the logic type, it makes suitable in implementing complicated logic expressions such as addition. In ADC power dissipation will occur only during the positive edge of clock cycle, in negative edge there will be no power consumption because system clock will act as Vdd supply for ACD. So this character will give advantage over static cmos and dynamic cmos logic style in terms of delay and CD logic in terms of power dissipation. Window factor has to be considered in order to attain the high performance digital blocks, the input has to be change only inside the window. Using general purpose cmos a full adder is designed and various analysis like delay, power consumption, and area. The result shows ACD logic has the minimum value for product of power and delay compare to other logic styles.