Influence of interface traps on the performance of Tunnel FETs

• Published in: 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S) p. 1
• Main Authors: Esseni, D., Pala, M., Gnani, E., Sangiorgi, E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2015
• Subjects: Current measurement; Electronic mail; Field effect transistors; Integrated circuit modeling; Power supplies
• DOI: 10.1109/E3S.2015.7336798

Summary form only given. Today Tunnel FETs are perceived as the most promising small slope transistors, that may enable a significant decrease in the power supply of integrated circuits and thus an improvement of their energy efficiency. However, many experimental results largely differ from the simulations of ideal Tunnel FETs, in fact simulations report small sub-threshold swing (SS) values over several orders of magnitudes of drain current, low off-current, and high on-current values, which, unfortunately, are not observed in experimental results. Such a discrepancy between simulated and experimental IV characteristics suggest that the modeling of idealized TFETs may be neglecting non-ideal effects that play an important role in measured devices. In this respect, several experimental papers made an explicit statement about the fact that the SS values observed in measured transistors are severely degraded by trap-assisted-tunneling (TAT) via interface or bulk traps. This problem may be particularly challenging in III-V based Tunnel FETS which, while they promise large tunneling currents thanks to the relatively small band-gap, may suffer of larger trap densities compared to Si or SiGe transistors.