A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper

We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (V MIN ). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bi...

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Published in2016 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1014 - 1017
Main Authors Chiu, Yi-Wei, Hu, Yu-Hao, Zhao, Jun-Kai, Jou, Shyh-Jye, Chuang, Ching-Te
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 01.05.2016
Subjects
Chip formation
Circuits
Design engineering
Design improvements
Electric potential
Frequency measurement
Leakage current
Leakage currents
Monte Carlo methods
Semiconductor device measurement
SRAM cells
Static random access memory
Transistors
Voltage
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Summary:We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (V MIN ). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read V MIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve V MIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 21% at low supply voltages.
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ISSN:2379-447X
DOI:10.1109/ISCAS.2016.7527415