Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs
Gate-all-around (GAA) transistors use multiple parallel nanowires to achieve the desired ON current. The fabrication and performance of GAA transistors have been reported, however, a fundamental consideration, namely, the scaling and variability of transistor performance as a function of the number...
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Published in | 2013 IEEE International Electron Devices Meeting pp. 7.5.1 - 7.5.4 |
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Main Authors | , , , , , , , |
Format | Conference Proceeding Journal Article |
Language | English |
Published |
IEEE
01.12.2013
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Subjects | |
Online Access | Get full text |
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Summary: | Gate-all-around (GAA) transistors use multiple parallel nanowires to achieve the desired ON current. The fabrication and performance of GAA transistors have been reported, however, a fundamental consideration, namely, the scaling and variability of transistor performance as a function of the number of parallel NWs is yet to be discussed. In this paper, we (i) examine how the overall performance matrix (e.g., I ON , I OFF , V th , SS, R C ) depends on the number of parallel NWs, (ii) theoretically interpret the results in terms of variability and self-heating among the NWs, (iii) compare the reliability of multiple NW devices (ΔV th , ΔSS, both stress and recovery) with a planar device of similar technology. We find that the self-heating and NW-to-NW variability are reflected in novel properties of variability and reliability of GAA transistors that are neither anticipated nor observed in the corresponding planar technology. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Conference-1 ObjectType-Feature-3 content type line 23 SourceType-Conference Papers & Proceedings-2 |
ISSN: | 0163-1918 2156-017X |
DOI: | 10.1109/IEDM.2013.6724582 |