Design of a robust and ultra-low-voltage pulse-triggered flip-flop in 28nm UTBB-FDSOI technology

So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operabi...

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Bibliographic Details
Published in2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) pp. 1 - 2
Main Authors Bernard, Sebastien, Valentian, Alexandre, Belleville, Marc, Bol, David, Legat, Jean-Didier
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2013
Subjects
Clocks
Delays
Latches
Pulse generation
Robustness
Threshold voltage
Voltage measurement
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Summary:So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operability of an energy-efficient pulsed-FF was validated at ultra-low operating supply voltage. Measurements of delays and correct functionality are performed in 28nm FDSOI technology. Then, the effect of back bias voltage, a key point in FDSOI technology, is studied and it is shown that our pulsed-FF reaches a minimum operating supply voltage of 170mV.
ISSN:1078-621X
2577-2295
DOI:10.1109/S3S.2013.6716555