III-V and Ge/strained SOI tunneling FET technologies for low power LSIs

We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/ III-V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs...

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Bibliographic Details
Published in2015 Symposium on VLSI Technology (VLSI Technology) pp. T22 - T23
Main Authors Takagi, S., Kim, M., Noguchi, M., Ji, S.-M, Nishi, K., Takenaka, M.
Format Conference Proceeding Journal Article
LanguageEnglish
Published JSAP 01.06.2015
Subjects
Channels
Diffusion
Germanium
Indium gallium arsenide
Junctions
Logic gates
Photonic band gap
Silicon
Slopes
Strain
Tunneling
Tunnels (transportation)
Zinc
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Summary:We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/ III-V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high I on /I off ratio over 10 7 and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found that I on and SS are improved by positive back bias. We have also demonstrated the operation of high I on /I off and low SS planar-type InGaAs Tunnel FETs with Zn-diffused source junctions. Solid-phase Zn diffusion can realize steep-profile and defect-less p + /n source junctions. The small S.S. of 64 mV/dec and large I on /I off ratio over 10 6 have been realized in the planar-type III-V TFETs.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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SourceType-Conference Papers & Proceedings-2
ISSN:0743-1562
2158-9682
DOI:10.1109/VLSIT.2015.7223687