Efficient scheduling scheme for eight-parallel MDC FFT processor

This paper presents a new eight-parallel multi-path delay commutator (MDC) FFT processor based on the novel modified radix-26 FFT algorithm. The proposed FFT processor can achieve a high throughput and a low hardware complexity by using the efficient scheduling scheme that reorders data-paths. The p...

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Bibliographic Details
Published in2015 International SoC Design Conference (ISOCC) pp. 277 - 278
Main Authors Jeong Keun Jang, Moon Gi Kim, Myung Hoon Sunwoo
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2015
Subjects
Algorithm design and analysis
Complexity theory
FFT
Hardware
MDC
OFDM
pipeline
Processor scheduling
Signal processing algorithms
Throughput
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Summary:This paper presents a new eight-parallel multi-path delay commutator (MDC) FFT processor based on the novel modified radix-26 FFT algorithm. The proposed FFT processor can achieve a high throughput and a low hardware complexity by using the efficient scheduling scheme that reorders data-paths. The proposed scheduling scheme and CSD approach can reduce the number of complex multipliers.
DOI:10.1109/ISOCC.2015.7401755