Design and VLSI implementation of high performance DUC and DDC for software defined radio applications

• Published in: 2013 International Conference on Emerging Trends in Communication, Control, Signal Processing and Computing Applications (C2SPCA) pp. 1 - 3
• Main Authors: Jyothi, N., Jayaprakash, S., Gowda, Shilpa K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2013
• Subjects: ADC - Analog to Digital converter; Band-pass filters; Baseband; CIC - Cascade Integrator Comb; DAC - Digital to Analog Converter; DDC - Digital Down Converter; DDS - Direct Digital synthesizer; DUC - Digital Up Converter; Field programmable gate arrays; Finite impulse response filters; FIR - Finite Impulse response; FPGA - Field Programmable Gate Array; Frequency modulation; HF - High Frequency; IF - Intermediate Frequency; Interpolation; Receivers
• ISBN: 9781479910823; 1479910821
• DOI: 10.1109/C2SPCA.2013.6749375

Paper deals with the implementation of high performance digital up converter and digital down converter for software defined radio application. Digital up converters are used at the transmitter side to up convert the baseband signal to intermediate frequency signal. Digital down converters are used at receiver side to down convert intermediate frequency signal to baseband signal. DUC and DDC modules are designed using System generator Xilinx block set and generated verilog code for the same. Simulation is performed using Isim and synthesis is carried out using Xilinx ISE 13.2. Design has implemented on vertex-4 FPGA board. The power consumed in this design is 52.6mWatts and the maximum operating frequency is up to 336.1MHz and total time taken for output is 2.93ns.