Variable-length gateless transistor for analog one-time-programmable memory applications

This work presents a novel embedded Analog Gateless One-Time-Programming Memory (AG-OTP), implemented by standard CMOS logic process. The NVM cell includes a gateless storage node in series with a select transistor; where the charge stored on the parasitic ONO structure. The p-channel device is prog...

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Published in2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) pp. 1 - 2
Main Authors Po-Ruei Cheng, Chih-Sung Yang, Meng-Yin Hsu, Chrong Jung Lin, Ya-Chin King
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2016
Subjects
CMOS integrated circuits
Current measurement
Dielectrics
Logic gates
Nonvolatile memory
Programming
Transistors
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Abstract This work presents a novel embedded Analog Gateless One-Time-Programming Memory (AG-OTP), implemented by standard CMOS logic process. The NVM cell includes a gateless storage node in series with a select transistor; where the charge stored on the parasitic ONO structure. The p-channel device is programmed by channel hot hole induced hot electron injection (CHHIHE). An angled-shaped source region allows the gateless channel to be partially turned-on and gradually increase the read current level. This unique structure enable the storage of analog data as continuous read current can be readily achieved.
AbstractList This work presents a novel embedded Analog Gateless One-Time-Programming Memory (AG-OTP), implemented by standard CMOS logic process. The NVM cell includes a gateless storage node in series with a select transistor; where the charge stored on the parasitic ONO structure. The p-channel device is programmed by channel hot hole induced hot electron injection (CHHIHE). An angled-shaped source region allows the gateless channel to be partially turned-on and gradually increase the read current level. This unique structure enable the storage of analog data as continuous read current can be readily achieved.
Author Ya-Chin King
Po-Ruei Cheng
Chih-Sung Yang
Meng-Yin Hsu
Chrong Jung Lin
Author_xml – sequence: 1
  surname: Po-Ruei Cheng
  fullname: Po-Ruei Cheng
  organization: Microelectron. Lab., Nat. Tsing Hua Univ., Hsinchu, Taiwan
– sequence: 2
  surname: Chih-Sung Yang
  fullname: Chih-Sung Yang
  organization: Microelectron. Lab., Nat. Tsing Hua Univ., Hsinchu, Taiwan
– sequence: 3
  surname: Meng-Yin Hsu
  fullname: Meng-Yin Hsu
  organization: Microelectron. Lab., Nat. Tsing Hua Univ., Hsinchu, Taiwan
– sequence: 4
  surname: Chrong Jung Lin
  fullname: Chrong Jung Lin
  organization: Microelectron. Lab., Nat. Tsing Hua Univ., Hsinchu, Taiwan
– sequence: 5
  surname: Ya-Chin King
  fullname: Ya-Chin King
  email: ycking@ee.nthu.edu.tw
  organization: Microelectron. Lab., Nat. Tsing Hua Univ., Hsinchu, Taiwan
BookMark eNotj8tqwzAURFVoF22aLygF_4BSPWxZWobQR8CQRdLQXbhWr12BHkbWJn_flGYxzOrMYR7IbUwRCXnmbMU5My_Hbr-lh_16JRhXq7bWrNbNDVmaVvNatdLUrTb35OsI2UHvkXqMY_mpRijocZ6rkiHObi4pV8MlEMGnsbpIaHEB6ZTTmCGEP7YKGFI-VzBN3lkoLsX5kdwN4GdcXntBPt9eD5sP2u3et5t1Rx0XstAaZc-1YL2AxvZcCZQIzA69GODbWmMEA8G1YnpQRltbD5YrxEZxzY3RRi7I0_-uQ8TTlF2AfD5d_8pfcdlSIg
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/VLSI-TSA.2016.7480485
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9781467394789
1467394785
EndPage 2
ExternalDocumentID 7480485
Genre orig-research
GroupedDBID 6IE
6IL
CBEJK
RIE
RIL
ID FETCH-LOGICAL-i123t-4e3b1820b2a5cb162e3ea0cfb2fadcc9920a218608f698cc4fc16ee5618199893
IEDL.DBID RIE
IngestDate Thu Jun 29 18:37:22 EDT 2023
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i123t-4e3b1820b2a5cb162e3ea0cfb2fadcc9920a218608f698cc4fc16ee5618199893
PageCount 2
ParticipantIDs ieee_primary_7480485
PublicationCentury 2000
PublicationDate 20160401
PublicationDateYYYYMMDD 2016-04-01
PublicationDate_xml – month: 04
  year: 2016
  text: 20160401
  day: 01
PublicationDecade 2010
PublicationTitle 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)
PublicationTitleAbbrev VLSI-TSA
PublicationYear 2016
Publisher IEEE
Publisher_xml – name: IEEE
Score 1.6449184
Snippet This work presents a novel embedded Analog Gateless One-Time-Programming Memory (AG-OTP), implemented by standard CMOS logic process. The NVM cell includes a...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms CMOS integrated circuits
Current measurement
Dielectrics
Logic gates
Nonvolatile memory
Programming
Transistors
Title Variable-length gateless transistor for analog one-time-programmable memory applications
URI https://ieeexplore.ieee.org/document/7480485
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3JTsMwELXanjgBahG7fOCI0yyOYx8RoiqIIqQu6q2ynbFA0BSh9ABfjycJZREHblGUOJYd-Y3H780j5CwyWeI3bJIZoXPGtXNMSpsyiESWxFmaqwj1zqM7MZzym3k6b5HzjRYGACryGQR4WZ3l5yu7xlRZP-PS_3Bpm7QzpWqtViPKiULVn92Or9lkfIF8LRE0z_4wTakwY7BNRp9fq6kiT8G6NIF9_1WI8b_d2SG9L3Uevd_gzi5pQdEl85nf9KIMiqE1SvlAMT327JcxWiIaVcVAqA9QqS4wXUNXBTD0lWcNQWuJ79Il8m7f6PdT7R6ZDq4ml0PWuCawR49CJeOQGKzKbmKdWhOJGBLQoXUmdjq3Vqk41GhEFUonlLSWOxsJAB9HSdTbqWSPdArfiX1CjUc4zX0LXFsOShsfjjudZU6K3IJJD0gXR2XxUhfGWDQDcvj37SOyhTNT016OSad8XcOJR_TSnFZT-QEFZqXm
link.rule.ids 310,311,783,787,792,793,799,27939,55088
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV09T8MwED2VMsAEqEV844ERp03iOM6IEFULbYXUD3WrbMcWCJoilA7w6_EloXyIgS2KEseyI7_z-b17ABe-ikO3YRNUcZlSJq2lQuiIGp_HYRBHaeKj3nkw5N0Ju51FsxpcrrUwxpiCfGY8vCzO8tOlXmGqrBUz4X64aAM2I4wrSrVWJcvx20lr2h_16Hh0hYwt7lVP_7BNKVCjswODz--VZJEnb5UrT7__KsX43w7tQvNLn0fu18izBzWTNWA2ddteFEJRNEfJHwgmyJ7dQkZyxKOiHAhxISqRGSZsyDIzFJ3laUXRWuC7ZIHM2zfy_Vy7CZPOzfi6SyvfBProcCinzIQK67KrQEZa-TwwoZFtbVVgZap1kgRtiVZUbWF5IrRmVvvcGBdJCVTcJeE-1DPXiQMgymGcZK4FJjUziVQuILcyjq3gqTYqOoQGjsr8pSyNMa8G5Ojv2-ew1R0P-vN-b3h3DNs4SyUJ5gTq-evKnDp8z9VZMa0f4EKpMw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2016+International+Symposium+on+VLSI+Technology%2C+Systems+and+Application+%28VLSI-TSA%29&rft.atitle=Variable-length+gateless+transistor+for+analog+one-time-programmable+memory+applications&rft.au=Po-Ruei+Cheng&rft.au=Chih-Sung+Yang&rft.au=Meng-Yin+Hsu&rft.au=Chrong+Jung+Lin&rft.date=2016-04-01&rft.pub=IEEE&rft.spage=1&rft.epage=2&rft_id=info:doi/10.1109%2FVLSI-TSA.2016.7480485&rft.externalDocID=7480485