Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics

• Published in: 2016 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 4
• Main Authors: Wang, Yuan, Liu, Yuequan, Jiang, Mengyin, Jia, Song, Zhang, Xing
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.05.2016
• Subjects: Circuits; Clocks; Coarsening; Delay; Delay lines; delay-locked loop (DLL); Delays; edge-combiner; eight-phase-clock generator; Electric potential; fast locking; FCC; Finishes; Generators; Locking; quadrupler; Tuning; Voltage control; wide operating range
• ISSN: 2379-447X
• DOI: 10.1109/ISCAS.2016.7527155

A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line, which uses four differential delay units to generate equally spaced eight-phase clocks. The coarse-code generator adopts a time-to-digital scheme to achieve short locking time and wide operating range. A fine-code digital-to-analog converter in the fine-code generator converts the fine codes to analog voltage for high precision. Moreover, the novel edge-combiner circuit combines the eight-phase clocks to x4 frequency output with 50% duty cycle ratio. Experimental results in a 65-nm CMOS process show this frequency multiplier can cover a frequency range from 320 MHz to 2.4 GHz and cost 5~40 cycles to finish locking.