Sniper-TEVR: Core-variation simulation platform with register-level fault injection for robust computing in CMP system

Technology scaling enables Chip Multiprocessors (CMPs) a promising approach to powerful performance within a chip. However, increasing transistor density makes them more susceptible to transient faults. Even worse, process variation due to unstable manufacturing makes the reliability problem more co...

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Bibliographic Details
Published in2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) pp. 1 - 4
Main Authors Ching-Yao Chou, Yi-Chieh Ho, Huai-Ting Li, An-Yeu Wu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2016
Subjects
Circuit faults
Computational modeling
Multicore processing
Redundancy
Registers
Robustness
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Summary:Technology scaling enables Chip Multiprocessors (CMPs) a promising approach to powerful performance within a chip. However, increasing transistor density makes them more susceptible to transient faults. Even worse, process variation due to unstable manufacturing makes the reliability problem more complicated. In recent years, there is a trend towards exploiting the inherent core redundancy characteristic in multi-core systems for error resilience. Nevertheless, traditional multi-core simulators lack of features to support reliability research. For fault environment simulation, high-level fault injection techniques make soft error effect unreal. Besides, core-variation error environment is not supported. For N Modular Redundancy (NMR) system simulation, there is no thread duplicate and thread affinity assignment feature. In this paper, we present a core-variation simulation platform with register-level fault injection based on intel's Sniper multi-core simulator. In addition to modifications of internal mechanism, an application program interface (API) is also provided. The validation result shows that the fault model in our simulator is consistent with exponential distribution model. In case study, NMR-system is validated. Hence, the proposed platform can be used for robust computing on multicore and other related researches in the future.
DOI:10.1109/VLSI-DAT.2016.7482558