Impact of Voltage Bias on Through Silicon Vias (TSV) depletion and crosstalk
In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear ph...
Saved in:
Published in | 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI) pp. 1 - 4 |
---|---|
Main Authors | , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.05.2016
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear phenomena and their combined impact on crosstalk among TSV and between TSVs and active circuits. |
---|---|
DOI: | 10.1109/SaPIW.2016.7496255 |