Impact of Voltage Bias on Through Silicon Vias (TSV) depletion and crosstalk

In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear ph...

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Bibliographic Details
Published in2016 IEEE 20th Workshop on Signal and Power Integrity (SPI) pp. 1 - 4
Main Authors Piersanti, S., de Paulis, F., Orlandi, A., Fan, J., Drewniak, J., Achkir, B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2016
Subjects
Capacitance
circuit modelin
Crosstalk
hysteresis
Integrated circuit modeling
non linear effects
segmentation
Silicon
Substrates
Three-dimensional displays
Through-silicon vias
TSVs Through Silicon Vias
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Summary:In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear phenomena and their combined impact on crosstalk among TSV and between TSVs and active circuits.
DOI:10.1109/SaPIW.2016.7496255