Challenges of design and packaging for 3D stacking with logic and DRAM dies

A Wide IO DRAM controller chip with Through Silicon Via (TSV) technology is implemented. Test circuitry for prebonding TSV tests are embedded in between the fine pitch TSVs. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance...

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Bibliographic Details
Published in2014 International Conference on Electronics Packaging (ICEP) pp. 448 - 451
Main Authors Fukuoka, Kazuki, Nii, Koji, Nomura, Takao, Mori, Ryo, Ochiai, Toshihiko, Takayanagi, Koji, Mori, Kentaro, Kida, Tsuyoshi, Morita, Sadayuki
Format Conference Proceeding
LanguageEnglish
Published JIEP 01.04.2014
Subjects
3D stacking
Bonding
fully digital noise monitor
impedance optimization
Monitoring
Noise
pre-bonding test
Random access memory
Stacking
switching noise
thermal issues
Three-dimensional displays
Through-silicon vias
TSV
void less underfill
Wide IO DRAM
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Summary:A Wide IO DRAM controller chip with Through Silicon Via (TSV) technology is implemented. Test circuitry for prebonding TSV tests are embedded in between the fine pitch TSVs. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital noise monitor. We also develop a 3D stacked flip chip assembly process with void less underfill enabled by Non Conductive Film (NCF). 12.8 GB/s operation is achieved, while IO power was reduced by 89% compared to LPDDR3.
DOI:10.1109/ICEP.2014.6826722