A probabilistic model for stuck-on faults in combinational logic gates

Reliability in advanced CMOS devices is a critical issue that can supersede the benefits of technology shrinking process. The Probabilistic Transfer Matrix (PTM) is the basis of more common reliability evaluation models. This work presents a probabilistic model for stuck-on faults in combinational l...

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Bibliographic Details
Published in2016 17th Latin-American Test Symposium (LATS) pp. 39 - 44
Main Authors Schivittz, Rafael B., Franco, Denis T., Meinhardt, Cristina, Butzen, Paulo F.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2016
Subjects
Circuit faults
CMOS
Integrated circuit modeling
Integrated circuit reliability
Logic gates
Probabilistic logic
PTM model
Reliability
Stuck-on faults
Transistors
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Summary:Reliability in advanced CMOS devices is a critical issue that can supersede the benefits of technology shrinking process. The Probabilistic Transfer Matrix (PTM) is the basis of more common reliability evaluation models. This work presents a probabilistic model for stuck-on faults in combinational logic gates, considering the individual fault probability of each logic function input vector. It shows that considering the same fault probability for all input vectors underestimates the input influence on the gate reliability. These probabilities can be used as inputs in PTM models to provide results that are more accurate and increase the circuit reliability.
DOI:10.1109/LATW.2016.7483337